Q. Why pTunerOPUSTM?

It is a versatile tool which helps with timing closure and/or lowering power with drive strength optimizations. It is minimally intrusive with the existing netlist and fits seamlessly with your existing design flow.

Q. What file inputs do you take?

Verilog netlist (.v), library files in liberty format (.lib), extracted parasitics (.spef), back-annotated switching activity (.saif) and design constraints (.sdc).

Q. What if one of the input files are missing?

The essential files are just the netlist and the libraries. You will need the constraints to specify clock, all others are optional.

Q. How will you determine switching activity if not provided?

pTunerOPUSTM propagates switching activity from input to output and hence the propagated activity is used for power calculations and logic propagation, if any.

Q. What if parasitics are not specified?

With no parasitic information, the tool assumes a Zero Wireload model and no loads at the gate/port outputs.

Q. How accurate is your timing engine?

We have an in-house timing engine that is equivalent to available commercial timing suites in reporting accurate timing information.

Q. How do you manage ip blocks or analog circuits?

pTunerOPUSTM assumes any ip blocks, analog circuits, RAM modules or any missing module as a blackbox and performs optimization without disturbing this module.

Q. Do you support false paths, multicycle paths and propagated constants?


Q. Do you identify false paths?

pTunerOPUSTM supports setting false paths and includes them in optimization but does not identify or locate them.

Q. How do you report errors?

pTunerOPUSTM generates a log file at the end of each run which holds a list of commands used in the run and another file that lists all the errors and warnings.

Q. Across what platforms is the tool compatible?

pTunerOPUSTM has been tested in Windows and major Linux distributions like CentOS, Ubuntu, SuSE, etc. in both 32 and 64 bit versions.

Q. What is the size of the binary?

Depending on the platform and features requested, it will be a few MegaBytes.

Q. How much time will each run take?

It is dependent on the type of circuit, on the kind of optimization run and the size of the netlist. The run time is generally orders of magnitude lower than standard place and route tools.

Q. Is there any re-placement of the netlist required? If yes, how much is the overall effect?

As pTunerOPUSTM functions best with incremental optimization over an optimized netlist, the floorplan remains the same. There might be a few changes and so re-placement is necessary but this should be a minor step in terms of time and overall displacement.

Q. What if timing is disturbed after optimization?

pTunerOPUSTM considers timing to be the highest priority when performing power optimizations – hence all the timing constraints are strictly observed.

Q. What are the outputs generated?

An optimized Verilog netlist (.v) is generated. Power, area and timing reports along with Detailed Cell Usage (DCU) reports can also be produced.

Q. Can the tool handle multiple thresholds and multiple voltages?

Yes – the tool can manage multiple thresholds but not multiple supply voltages.

Q. What about multiple clock domains, derived and generated clocks?

pTunerOPUSTM can handle multiple clock domains and all kinds of generated clocks.

Q. Where in the design flow will this tool fit?

pTunerOPUSTM can be used post-synthesis, pre-layout for a quick estimate and optimization for power or post-layout, before final verification for a pre-fabrication optimization run.

Q. Will the tool work with FINFET technology?

pTunerOPUSTM has been tested with both – standard cell CMOS and FINFET libraries.

Q. Who are your clients and what are the results?

We are currently engaged with a couple of companies and have good preliminary results with one showing an improvement of close to 10%.

Copyright © 2018 SAI