pTunerOPUS™ is an EDA tool providing power optimization within your existing design flow and works without altering the existing floorplan.

DESIGN FLOW with pTunerOPUSTM

pTunerOPUS™ can be used post-synthesis & pre-layout for a quick estimate and optimization for power or post-layout, before final verification & pre-fabrication optimization run.

pTunerOPUS™ combines advanced mathematical techniques with proprietary models and algorithms to deliver best-in-class optimization results.

pTunerOPUSTM UTILITY FLOW

We will engage under a license or services model, depending on our customers' design needs.

Characteristics

Supports hierarchical and flattened  netlist. Thus, individual blocks can be  optimized separately and custom IP  blocks  can be included as "black-boxes" into the  design flow.

Low execution time provides rapid feedback  during tradeoff analysis; resulting in better  design choices.

Power savings are independent-of & additive to existing commercial optimization tools.

Takes standard  design  synthesis files to optimize independently for dynamic and leakage or total power.

Supports multi-threshold standard cell libraries.

Supports multiple primary and generated clocks within a design.

Does not change circuit structure, so previously  generated floorplan  can be re-used.

Supports  command-line  as well as graphical user interface.

Perfect for IoT Market Requirements

Low Power                  

Low Cost                       

Time to Market          

Security                        …

INPUT

Standard Cell Libraries (.lib)

Gate-level verilog netlist (.v)

User-defined Timing Constraints (.sdc)

Back-annotated Parasitics (.spef) - optional

User-defined Switching Activity (.saif) - optional

OUTPUT

Optimized Gate-level verilog netlist (.v)

Timing, Area & Power reports (.txt)

Detailed Cell Usage report (.csv)

 

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