Supports hierarchical and flattened netlist. Thus, individual blocks can be optimized separately and custom IP blocks can be included as “black-boxes” into the design flow.
Low execution time provides rapid feedback during tradeoff analysis; resulting in better design choices.
Power savings are independent-of & additive to existing commercial optimization tools.
Takes standard design synthesis files to optimize independently for dynamic and leakage or total power.
Supports multi-threshold standard cell libraries.
Supports multiple primary and generated clocks within a design.
Does not change circuit structure, so previously generated floorplan can be re-used.
Supports command-line as well as graphical user interface.
Perfect for IoT Market Requirements
Low Power ✓
Low Cost ✓
Time to Market ✓
Standard Cell Libraries (.lib)
Gate-level verilog netlist (.v)
User-defined Timing Constraints (.sdc)
Back-annotated Parasitics (.spef) – optional
User-defined Switching Activity (.saif) – optional
Optimized Gate-level verilog netlist (.v)
Timing, Area & Power reports (.txt)
Detailed Cell Usage report (.csv)